Sorry people!
I just wanted to share that testing and i didn´t want to insult anyone, i just was angry because i thought we where in the wrong path.
As you said Russ, testing is needed to see what happens, testing is the only one that will show us the path :)

Quote from Jeff Nading on May 12th, 2012, 07:28 AM

Quote from ~Russ/Rwg42985 on May 11th, 2012, 11:23 PM

Quote from Jeff Nading on May 11th, 2012, 12:50 PM

Quote from Muxar on May 11th, 2012, 11:31 AM

Bad news people!!
It looks like this annoying guy was rigth about the gab betwen the cores:

https://www.youtube.com/watch?v=EHbFm7ylHY4
look what hapens with and without the gab:

https://www.youtube.com/watch?v=QlWXb3oC4rs

Guy's, don't worry about Max videos, everything is under control, we need to see for ourselves if there is a gap or not, Russ say's no gap so I think we should go with that. Also, if there is proof that we need a gap we can cut one, not a problem, but think if there is no gap and we had a gap made in the cores, we would be up a creek without a paddle so to speak, so let use our own resources and not someone else's. Yes I put out the same question to Russ, and I concluded Russ was right, thanks ,guy's.:D

like i stated in one of my videos, dont madder who gets it going... just do it and show how, as we all need to try deterrent stuff to get this to work...

gap, no gap...

here is why i state no gap,

i taked to Don, the man who took these photos and took the measurements and had these things in his hands.  we have had Manny phone conversations, i trust what he tells me to be valid information based on the information researched.

Don took off some silicone that was covering the hole where you can see a gap. interestingly Don stated that there was no gap or no "shim" in between the cores...   he also stated that all the coils were not bolted down, just floating there... like one had tampered with the VIC coils... some of the photos were taken after don had taken the coils apart... thus a gap is shown...  

i'm glad max is trying the gap, this will make or brake this coil set. just like the no gap. one must try it all!!!!

From the data i have collected and some others i dont think there is a gap... know one can be for sure...

the VIC may work with or with out the gap depending on the core... who knows!

jeff,

we can watch what max has to say as we are all in the same boat, ALL of us...

ALL:

if you have negative things to say about others please just stick to the DATA and not the EGO. bring forth the information presented and keep personal conflict out. it would make everything better in the long run! again, as discussed before, lets keep it positive and keep pushing this tech forward! its not about who... its about the tech at hand...

last:

i'm just one of you guys... just because i say or i think something is true or what ever dose not mean I'm right. this is all up in there air for discussion!!! including what others have to say, that includes max, he is welcome here and would love to see him post his thoughts and have a healthy discussion,  as know one has all the answers... just there best educated guess.  

and last... GOD BLESS!!! :)

~Russ

Sorry Russ, you are very right, sorry guy,s and Max.:blush::blush:

Quote from Muxar on May 12th, 2012, 08:23 AM

Sorry people!
I just wanted to share that testing and i didn´t want to insult anyone, i just was angry because i thought we where in the wrong path.
As you said Russ, testing is needed to see what happens, testing is the only one that will show us the path :)

Quote from Jeff Nading on May 12th, 2012, 07:28 AM

Quote from ~Russ/Rwg42985 on May 11th, 2012, 11:23 PM

Quote from Jeff Nading on May 11th, 2012, 12:50 PM

Quote from Muxar on May 11th, 2012, 11:31 AM

Bad news people!!
It looks like this annoying guy was rigth about the gab betwen the cores:

https://www.youtube.com/watch?v=EHbFm7ylHY4
look what hapens with and without the gab:

https://www.youtube.com/watch?v=QlWXb3oC4rs

Guy's, don't worry about Max videos, everything is under control, we need to see for ourselves if there is a gap or not, Russ say's no gap so I think we should go with that. Also, if there is proof that we need a gap we can cut one, not a problem, but think if there is no gap and we had a gap made in the cores, we would be up a creek without a paddle so to speak, so let use our own resources and not someone else's. Yes I put out the same question to Russ, and I concluded Russ was right, thanks ,guy's.:D

like i stated in one of my videos, dont madder who gets it going... just do it and show how, as we all need to try deterrent stuff to get this to work...

gap, no gap...

here is why i state no gap,

i taked to Don, the man who took these photos and took the measurements and had these things in his hands.  we have had Manny phone conversations, i trust what he tells me to be valid information based on the information researched.

Don took off some silicone that was covering the hole where you can see a gap. interestingly Don stated that there was no gap or no "shim" in between the cores...   he also stated that all the coils were not bolted down, just floating there... like one had tampered with the VIC coils... some of the photos were taken after don had taken the coils apart... thus a gap is shown...  

i'm glad max is trying the gap, this will make or brake this coil set. just like the no gap. one must try it all!!!!

From the data i have collected and some others i dont think there is a gap... know one can be for sure...

the VIC may work with or with out the gap depending on the core... who knows!

jeff,

we can watch what max has to say as we are all in the same boat, ALL of us...

ALL:

if you have negative things to say about others please just stick to the DATA and not the EGO. bring forth the information presented and keep personal conflict out. it would make everything better in the long run! again, as discussed before, lets keep it positive and keep pushing this tech forward! its not about who... its about the tech at hand...

last:

i'm just one of you guys... just because i say or i think something is true or what ever dose not mean I'm right. this is all up in there air for discussion!!! including what others have to say, that includes max, he is welcome here and would love to see him post his thoughts and have a healthy discussion,  as know one has all the answers... just there best educated guess.  

and last... GOD BLESS!!! :)

~Russ

Sorry Russ, you are very right, sorry guy,s and Max.:blush::blush:

We all are in this together,    Muxar and we are all imperfect, as am I, make mistakes everyday, i am sorry to, Jeff.:D

Quote from Quantum on May 5th, 2012, 07:53 AM

Hi all!

I will try to answer your question: "We need the feedback pulse also to have 50% duty cycle, this is when you have resonance (total resonance etc. ) ??"

As I understand the working of 4046, I think when the feedback signals on the pin 14 and 3 are exactly the same frequency and phase, the output pins 1 and 2 will be in low state resulting the UD7 4001 NOR gate output to be in high state. This will occur only when the circuit has found the resonance. If I am wrong let me know.

Peace

You're wrong:
The logic is reversed, the diagram is right.
I tested: when the line is okay, CP1 (pin 2) is half time "1" and LD (pin 1) is 99.9% "1".
This data sheet (4046) shows that you, not exactly the same, but I think it works the same.[/quote]

Quote from Sharky on May 11th, 2012, 04:55 AM

Uploaded  VIC1.1-20120511.zip to the first post. It contains the corrected error and track changes for the pcb. I want to add the pot meters again to the 4046 to be able to finetune its min/max frequency settings.

Good continuing:
After reading a comment of the TonyWoodside, about 4017 and her pulses are not square, it was an insight I had. Well so far made ​​no sense, as the PLL detect the resonance through the Pc2, as I had observed this comparator (PC2) does not respond as PC1 (ok dphi = 90 °), therefore, and the way that the diagram "vicschem "even without using one of three" 4017 "(this is divided by 10), does not really make sense.
Now, off pins 4 and 3 (4046) and using (at least one) of 4017 and taking the signal output by any of the "Q" (q0, q1, q2, .... q9), we have a pulse with a pulse full width of the VCO and repeated every 10. In other words, f out = 1/10 and duty = 1/10, thus uses less power, less current (like PWM), but being tuned the VIC, to reproduce the wave symmetric and FB picks up a square wave, satisfying the "PC2" .
4017 can be used (N/10) or 4022 (N / 8). Meyer did not say which he used.
The VCO should be adjusted to a range much higher, eg. (in 4022):
VCO = 51.2 kHz__768kHz
(after N / 8) = 6.4 kHz__96kHz
(after N / 8) = 800Hz__12kHz
(after N / 8) = 100Hz__1, 5kHz

Another example. (in 4017):
VCO = 60kHz__720kHz
(after N/10) = 6kHz__72kHz
(after N/10) = 600Hz__7, 2kHz
(after N/10) = 60Hz__720Hz
This can be tested in many ways. Note that the overlapping end of one range to the next.
I believe the higher range (direct VCO) will not be used (perhaps only for testing).
In their tests will use the middle of the range = 2.5 kHz, then VCO = 25kHz (4017) or = 20 kHz (4022)
This works, I tried!
Someone comments?
Congratulations to all, are doing a good job.
My name is Fidel

Ok, getting back to what this thread was all about ;) ... I will try and squeeze in 3 switches implemented as jumpers on the pcb. One at the gating output, one between the 4046 and the cell driver and one between voltage amplitude control and primairy. That way we can easily exchange or reuse those parts. I will look into the divider thing but your post is not very clear to me ? The dividers were not connected on the meyer vic version, can you and elaborate on what you meant to point out?
Regards,
Sharky

Quote from Faisca on May 12th, 2012, 09:06 AM

Quote from Quantum on May 5th, 2012, 07:53 AM

Hi all!

I will try to answer your question: "We need the feedback pulse also to have 50% duty cycle, this is when you have resonance (total resonance etc. ) ??"

As I understand the working of 4046, I think when the feedback signals on the pin 14 and 3 are exactly the same frequency and phase, the output pins 1 and 2 will be in low state resulting the UD7 4001 NOR gate output to be in high state. This will occur only when the circuit has found the resonance. If I am wrong let me know.

Peace

You're wrong:
The logic is reversed, the diagram is right.
I tested: when the line is okay, CP1 (pin 2) is half time "1" and LD (pin 1) is 99.9% "1".
This data sheet (4046) shows that you, not exactly the same, but I think it works the same.

[/quote]Thx mate. So you tested with continuous or gated pulses? Some people are having problems locking in with gated pulses. Is it ok for you?

Quote from Sharky on May 13th, 2012, 03:23 AM

Ok, getting back to what this thread was all about ;) ... I will try and squeeze in 3 switches implemented as jumpers on the pcb. One at the gating output, one between the 4046 and the cell driver and one between voltage amplitude control and primairy. That way we can easily exchange or reuse those parts. I will look into the divider thing but your post is not very clear to me ? The dividers were not connected on the meyer vic version, can you and elaborate on what you meant to point out?
Regards,
Sharky

You got me wrong, the original Meyer uses dividers, in your diagram they are not being used. The VCO (pin 4) is direct PCB (pin 3) is wrong.
I will make a diagram and oscillograms shots, to show more clearly. (not today).
See you soon.

Quote from Quantum on May 13th, 2012, 05:06 AM

Quote from Faisca on May 12th, 2012, 09:06 AM

Quote from Quantum on May 5th, 2012, 07:53 AM

Hi all!

I will try to answer your question: "We need the feedback pulse also to have 50% duty cycle, this is when you have resonance (total resonance etc. ) ??"

As I understand the working of 4046, I think when the feedback signals on the pin 14 and 3 are exactly the same frequency and phase, the output pins 1 and 2 will be in low state resulting the UD7 4001 NOR gate output to be in high state. This will occur only when the circuit has found the resonance. If I am wrong let me know.

Peace

You're wrong:
The logic is reversed, the diagram is right.
I tested: when the line is okay, CP1 (pin 2) is half time "1" and LD (pin 1) is 99.9% "1".
This data sheet (4046) shows that you, not exactly the same, but I think it works the same.

Thx mate. So you tested with continuous or gated pulses? Some people are having problems locking in with gated pulses. Is it ok for you?[/quote]Only continuous pulses, no gate.
This part of the "gate inhibit PLL" is not clear. It makes no sense, not yet. But we understand. (may be misinformation).
See you soon.

Quote from Faisca on May 13th, 2012, 12:43 PM

Quote from Sharky on May 13th, 2012, 03:23 AM

Ok, getting back to what this thread was all about ;) ... I will try and squeeze in 3 switches implemented as jumpers on the pcb. One at the gating output, one between the 4046 and the cell driver and one between voltage amplitude control and primairy. That way we can easily exchange or reuse those parts. I will look into the divider thing but your post is not very clear to me ? The dividers were not connected on the meyer vic version, can you and elaborate on what you meant to point out?
Regards,
Sharky

You got me wrong, the original Meyer uses dividers, in your diagram they are not being used. The VCO (pin 4) is direct PCB (pin 3) is wrong.
I will make a diagram and oscillograms shots, to show more clearly. (not today).
See you soon.

Quote from Quantum on May 13th, 2012, 05:06 AM

Quote from Faisca on May 12th, 2012, 09:06 AM

Quote from Quantum on May 5th, 2012, 07:53 AM

Hi all!

I will try to answer your question: "We need the feedback pulse also to have 50% duty cycle, this is when you have resonance (total resonance etc. ) ??"

As I understand the working of 4046, I think when the feedback signals on the pin 14 and 3 are exactly the same frequency and phase, the output pins 1 and 2 will be in low state resulting the UD7 4001 NOR gate output to be in high state. This will occur only when the circuit has found the resonance. If I am wrong let me know.

Peace

You're wrong:
The logic is reversed, the diagram is right.
I tested: when the line is okay, CP1 (pin 2) is half time "1" and LD (pin 1) is 99.9% "1".
This data sheet (4046) shows that you, not exactly the same, but I think it works the same.

Thx mate. So you tested with continuous or gated pulses? Some people are having problems locking in with gated pulses. Is it ok for you?

Only continuous pulses, no gate.
This part of the "gate inhibit PLL" is not clear. It makes no sense, not yet. But we understand. (may be misinformation).
See you soon.

Hi,

The 4017 are not used for the PLL. Only as dividers for the led.
If your frequency is max 10khz and divide to 10 hz max you can still see the led flashing as indicator.

My thoughts.

See photo from Dynodon where light is under the pcb so you can see the layers. The pin 4 PLL, is rewired also pin 3. Dividers are bypassed as total signal.

Br,
Webmug

Quote from Webmug on May 13th, 2012, 02:08 PM

Hi,

The 4017 are not used for the PLL. Only as dividers for the led.
If your frequency is max 10khz and divide to 10 hz max you can still see the led flashing as indicator.

My thoughts.

See photo from Dynodon where light is under the pcb so you can see the layers. The pin 4 PLL, is rewired also pin 3. Dividers are bypassed as total signal.

Br,
Webmug

I agree with webmug. Looking at the original PCB photos from Dynodon i concluded that the dividers were only used for the led, that is why we left it out. Possibly it was put in at first because the frequency range was not known yet, anyway remember the vic pcb was still a systems development version and contains things that serve no purpose. On the feedback signal, .... to my understanding the feedback signal does not need to have 50% dutycycle for the vco output to be 50% dutycycle. It will lock on to the phase of the signal to get its frequency but a short pulse should already be sufficient, .... at least that is what i make up from the 4046 datasheet.

On the gating, ... the pulses from the feedback signal extend beyond the vco output. What i mean by that is when the gating kicks in the vco output is set low. Coil resonance however will cause a continuing energy exchange between the coils and capacitor, ... that is what is called resonance. So even when gating is on the feedback signal will continue to produce pulses as long as its amplitude is above the opamp minimum. So i think that if gating is too long it will loose its lock as soon as the amplitude gets below the minimum but if we adjust gating to the point where it still produces sufficient feedback signal it should work fine. Maybe that is meant by tuning in to the resonant action?

Quote from Sharky on May 14th, 2012, 02:33 AM

...

On the gating, ... the pulses from the feedback signal extend beyond the vco output. What i mean by that is when the gating kicks in the vco output is set low. Coil resonance however will cause a continuing energy exchange between the coils and capacitor, ... that is what is called resonance. So even when gating is on the feedback signal will continue to produce pulses as long as its amplitude is above the opamp minimum. So i think that if gating is too long it will loose its lock as soon as the amplitude gets below the minimum but if we adjust gating to the point where it still produces sufficient feedback signal it should work fine. Maybe that is meant by tuning in to the resonant action?

you are pointing at a serious design issue!

that´s exactly the problem I ran into with my freedom circuit Stan Meyer  4046 rebuild 2 years ago. quite the same circuit design as you are using now. and that´s an important reason why I prefer a µC PLL solution:

1. maybe the coil oscillation while gating has another (higher) frequency than pulsing frequency (higher mode). then 4046 will get a wrong sync signal.

2. when 4046 loses feedback pulse it will restart oscillation after end of gating at minimum adjusted frequency and resynchronize with resonance after some time. that reduces resonant action time frame until next gating takes place. and that means that primary pulse voltage must be reduced for that period of time if VIC wire diameter is designed for operation in resonant condition.

a µC can remember last oscillation frequency and be instantaneously synchronized because it controlles frequency and gating. that´s the way the µC works I´m using.
so I have full control over frequency, resonance detection and gating all the time :-). there is a pulse out signal in non resonant condition and another pulse out for resonant condition. that way one mosfet can pulse with reduced input voltage to go for resonance and another mosfet can pulse full power at resonant condition.

I ran into the same problems you are discussing here and there was no way to go with 4046 in lock mode gating configuration.

maybe you can solve the problem by disconnecting the totem pole connector of 4046 while gating and then the relevant capacitor will preserve its voltage level for some time and maybe until gating is done and then 4046 jumps in at the recent lock frequency. but that takes a brief design review for 4046 configuration and lots of testing before buiding another pcb.

Quote from bussi04 on May 14th, 2012, 03:41 AM

Quote from Sharky on May 14th, 2012, 02:33 AM

...

On the gating, ... the pulses from the feedback signal extend beyond the vco output. What i mean by that is when the gating kicks in the vco output is set low. Coil resonance however will cause a continuing energy exchange between the coils and capacitor, ... that is what is called resonance. So even when gating is on the feedback signal will continue to produce pulses as long as its amplitude is above the opamp minimum. So i think that if gating is too long it will loose its lock as soon as the amplitude gets below the minimum but if we adjust gating to the point where it still produces sufficient feedback signal it should work fine. Maybe that is meant by tuning in to the resonant action?

you are pointing at a serious design issue!

that´s exactly the problem I ran into with my freedom circuit Stan Meyer  4046 rebuild 2 years ago. quite the same circuit design as you are using now. and that´s an important reason why I prefer a µC PLL solution:

1. maybe the coil oscillation while gating has another (higher) frequency than pulsing frequency (higher mode). then 4046 will get a wrong sync signal.

2. when 4046 loses feedback pulse it will restart oscillation after end of gating at minimum adjusted frequency and resynchronize with resonance after some time. that reduces resonant action time frame until next gating takes place. and that means that primary pulse voltage must be reduced for that period of time if VIC wire diameter is designed for operation in resonant condition.

a µC can remember last oscillation frequency and be instantaneously synchronized because it controlles frequency and gating. that´s the way the µC works I´m using.
so I have full control over frequency, resonance detection and gating all the time :-). there is a pulse out signal in non resonant condition and another pulse out for resonant condition. that way one mosfet can pulse with reduced input voltage to go for resonance and another mosfet can pulse full power at resonant condition.

I ran into the same problems you are discussing here and there was no way to go with 4046 in lock mode gating configuration.

maybe you can solve the problem by disconnecting the totem pole connector of 4046 while gating and then the relevant capacitor will preserve its voltage level for some time and maybe until gating is done and then 4046 jumps in at the recent lock frequency. but that takes a brief design review for 4046 configuration and lots of testing before buiding another pcb.

Hi,

I find it interesting if you are using a uC for the circuit.
Please post it in VIC2.0 PCB design ideas, if you want...:cool:

But using the 4046 there is also the scanner circuit. This is why it is so fast scanning for the resonance. The gating frequency is not know yet, but it seems it is slow, say 0.5 to 3 seconds, you want a fast lock-in after gate duty cycle.

Br,
Webmug

Just uploaded the final v1.1 files (KiCAD project, PDF and Gerber/Drill files). I removed the work in progess from the subject as for me this job is done. As busi and others recently pointed out there may still be some issues with gating or other. The goal however was to replicate the meyer board as close as possible. As this last board version contains several possibilities to change or replace several parts of the pcb i think that for now it is job done and sufficient to do some baseline testing. The results of those tests will most probably result in changes but lets incorporate those in a V2.0 vic.
Enjoy,
Sharky

Quote from Sharky on May 14th, 2012, 06:35 AM

Just uploaded the final v1.1 files (KiCAD project, PDF and Gerber/Drill files). I removed the work in progess from the subject as for me this job is done. As busi and others recently pointed out there may still be some issues with gating or other. The goal however was to replicate the meyer board as close as possible. As this last board version contains several possibilities to change or replace several parts of the pcb i think that for now it is job done and sufficient to do some baseline testing. The results of those tests will most probably result in changes but lets incorporate those in a V2.0 vic.
Enjoy,
Sharky

Very nice job Sharky, very cool.:cool::D:P

Only continuous pulses, no gate.
This part of the "gate inhibit PLL" is not clear. It makes no sense, not yet. But we understand. (may be misinformation).
See you soon.[/quote]Hi,

The 4017 are not used for the PLL. Only as dividers for the led.
If your frequency is max 10khz and divide to 10 hz max you can still see the led flashing as indicator.

My thoughts.

See photo from Dynodon where light is under the pcb so you can see the layers. The pin 4 PLL, is rewired also pin 3. Dividers are bypassed as total signal.

Br,
Webmug[/quote]Precisely this is wrong, think it is just to flash the LED.
Look at the diagram of Meyer (figara 7..PCT/US90/06407), the four-position rotary switch (sel range.), Only the first position, the divisor is ignored (I think it's the "0" = start ) and further a = 1/10 2 = 1/100 = 3 1/100.
With this arrangement the driver always wore a tenth of the power to avoid saturating the VIC and ensuring that the FB only produced a square wave, when you get resonance.
The other way, ignoring the divisor, the PLL will lock onto any frequency driver and 50% will always be excited and perhaps saturated.
This makes sense to you?
I'm confirming this in protoboard. It's real!

Success for us all.

Quote from Faisca on May 14th, 2012, 11:32 AM

Precisely this is wrong, think it is just to flash the LED.
Look at the diagram of Meyer (figara 7..PCT/US90/06407), the four-position rotary switch (sel range.), Only the first position, the divisor is ignored (I think it's the "0" = start ) and further a = 1/10 2 = 1/100 = 3 1/100.
With this arrangement the driver always wore a tenth of the power to avoid saturating the VIC and ensuring that the FB only produced a square wave, when you get resonance.
The other way, ignoring the divisor, the PLL will lock onto any frequency driver and 50% will always be excited and perhaps saturated.
This makes sense to you?
I'm confirming this in protoboard. It's real!

Success for us all.

"With this arrangement the driver always wore a tenth of the power to avoid saturating the VIC and ensuring that the FB only produced a square wave, when you get resonance" I don't follow.

I'm looking at three versions of the circuit! :huh: and I'm getting confused here...

Br,
Webmug

Quote from Webmug on May 14th, 2012, 04:29 AM

Quote from bussi04 on May 14th, 2012, 03:41 AM

Quote from Sharky on May 14th, 2012, 02:33 AM

...

On the gating, ... the pulses from the feedback signal extend beyond the vco output. What i mean by that is when the gating kicks in the vco output is set low. Coil resonance however will cause a continuing energy exchange between the coils and capacitor, ... that is what is called resonance. So even when gating is on the feedback signal will continue to produce pulses as long as its amplitude is above the opamp minimum. So i think that if gating is too long it will loose its lock as soon as the amplitude gets below the minimum but if we adjust gating to the point where it still produces sufficient feedback signal it should work fine. Maybe that is meant by tuning in to the resonant action?

you are pointing at a serious design issue!

that´s exactly the problem I ran into with my freedom circuit Stan Meyer  4046 rebuild 2 years ago. quite the same circuit design as you are using now. and that´s an important reason why I prefer a µC PLL solution:

1. maybe the coil oscillation while gating has another (higher) frequency than pulsing frequency (higher mode). then 4046 will get a wrong sync signal.

2. when 4046 loses feedback pulse it will restart oscillation after end of gating at minimum adjusted frequency and resynchronize with resonance after some time. that reduces resonant action time frame until next gating takes place. and that means that primary pulse voltage must be reduced for that period of time if VIC wire diameter is designed for operation in resonant condition.

a µC can remember last oscillation frequency and be instantaneously synchronized because it controlles frequency and gating. that´s the way the µC works I´m using.
so I have full control over frequency, resonance detection and gating all the time :-). there is a pulse out signal in non resonant condition and another pulse out for resonant condition. that way one mosfet can pulse with reduced input voltage to go for resonance and another mosfet can pulse full power at resonant condition.

I ran into the same problems you are discussing here and there was no way to go with 4046 in lock mode gating configuration.

maybe you can solve the problem by disconnecting the totem pole connector of 4046 while gating and then the relevant capacitor will preserve its voltage level for some time and maybe until gating is done and then 4046 jumps in at the recent lock frequency. but that takes a brief design review for 4046 configuration and lots of testing before buiding another pcb.

Hi,

I find it interesting if you are using a uC for the circuit.
Please post it in VIC2.0 PCB design ideas, if you want...:cool:

But using the 4046 there is also the scanner circuit. This is why it is so fast scanning for the resonance. The gating frequency is not know yet, but it seems it is slow, say 0.5 to 3 seconds, you want a fast lock-in after gate duty cycle.

Br,
Webmug

I agree with Sharky: Good hypotheses about what happens during the gate "oscillating remnant." It makes perfect sense.
About uC solution, this has always been my choice and we know who had been much better than the version of Meyer, he used the best we had at that time. Today we have much more than one hundred times the minimum.
But all agreed to re-produce the original Meyer and the database to build a new improved circuit.
I already have done three versions uC circuits (PIC 12F675) with and without crystal / clock, very small. Without scanning, resonance lock instantly. time spent = one period to catch a new wave. It seems to be perfect, but I do not know exactly how everything happened in the Meyer.
I think a good idea is a hybrid "uC + 4046", making 4046 a Peripheral uC.
Our success.

Quote from Webmug on May 14th, 2012, 12:06 PM

Quote from Faisca on May 14th, 2012, 11:32 AM

Precisely this is wrong, think it is just to flash the LED.
Look at the diagram of Meyer (figara 7..PCT/US90/06407), the four-position rotary switch (sel range.), Only the first position, the divisor is ignored (I think it's the "0" = start ) and further a = 1/10 2 = 1/100 = 3 1/100.
With this arrangement the driver always wore a tenth of the power to avoid saturating the VIC and ensuring that the FB only produced a square wave, when you get resonance.
The other way, ignoring the divisor, the PLL will lock onto any frequency driver and 50% will always be excited and perhaps saturated.
This makes sense to you?
I'm confirming this in protoboard. It's real!

Success for us all.

"With this arrangement the driver always wore a tenth of the power to avoid saturating the VIC and ensuring that the FB only produced a square wave, when you get resonance" I don't follow.

I'm looking at three versions of the circuit! :huh: and I'm getting confused here...

Br,
Webmug

Which three?
I only refer to the Meyer!

Hi Bussi04,
would it be possible to have a circuit diagram of how the uC and pll are connected in your circuit? It would be most useful for adapting to other uC boards like the arduino
thanks

Quote from Faisca on May 14th, 2012, 05:04 PM

Quote from Webmug on May 14th, 2012, 12:06 PM

Quote from Faisca on May 14th, 2012, 11:32 AM

Precisely this is wrong, think it is just to flash the LED.
Look at the diagram of Meyer (figara 7..PCT/US90/06407), the four-position rotary switch (sel range.), Only the first position, the divisor is ignored (I think it's the "0" = start ) and further a = 1/10 2 = 1/100 = 3 1/100.
With this arrangement the driver always wore a tenth of the power to avoid saturating the VIC and ensuring that the FB only produced a square wave, when you get resonance.
The other way, ignoring the divisor, the PLL will lock onto any frequency driver and 50% will always be excited and perhaps saturated.
This makes sense to you?
I'm confirming this in protoboard. It's real!

Success for us all.

"With this arrangement the driver always wore a tenth of the power to avoid saturating the VIC and ensuring that the FB only produced a square wave, when you get resonance" I don't follow.

I'm looking at three versions of the circuit! :huh: and I'm getting confused here...

Br,
Webmug

Which three?
I only refer to the Meyer!

1. PCT/US90/06407 patent (no TIP120 pickup, 4017, FB)
2. Dynodon photo circuit (TIP120 pickup, FB, no 4017)
3. RWG VIC1.0, VIC1.1 PCB (Sharky) (TIP120 pickup, FB, no 4017)

No switch or 4017 attached in the Photo at the PLL. Pll pin 4. is bypassed. pll pin 3 goes to the driver circuit.

Br,
Webmug

Which three?
I only refer to the Meyer![/quote]1. PCT/US90/06407 patent (no TIP120 pickup, 4017, FB)
2. Dynodon photo circuit (TIP120 pickup, FB, no 4017)
3. RWG VIC1.0, VIC1.1 PCB (Sharky) (TIP120 pickup, FB, no 4017)

No switch or 4017 attached in the Photo at the PLL. Pll pin 4. is bypassed. pll pin 3 goes to the driver circuit.

Br,
Webmug[/quote]sorry I had not seen this picture yet.
If this is really original PCB S.Meyer I'm wrong, but where these wires are attached?
How did this stuff (pictures)?
Anyway are not linked together pins 3 and 4 in the PLL, right?
Thank you.

Quote from Faisca on May 15th, 2012, 09:26 AM

Quote

Which three?
I only refer to the Meyer!

Quote

1. PCT/US90/06407 patent (no TIP120 pickup, 4017, FB)
2. Dynodon photo circuit (TIP120 pickup, FB, no 4017)
3. RWG VIC1.0, VIC1.1 PCB (Sharky) (TIP120 pickup, FB, no 4017)

No switch or 4017 attached in the Photo at the PLL. Pll pin 4. is bypassed. pll pin 3 goes to the driver circuit.

Br,
Webmug

Quote

sorry I had not seen this picture yet.
If this is really original PCB S.Meyer I'm wrong, but where these wires are attached?
How did this stuff (pictures)?
Anyway are not linked together pins 3 and 4 in the PLL, right?
Thank you.

http://open-source-energy.org/rwg42985/russ/Stans%20Estate/meyers%20pics%20%2863%29.JPG
http://open-source-energy.org/rwg42985/russ/Stans%20Estate/meyers%20pics%20%2868%29.JPG
More detail, the pll pin4. goes to the cell driver circuit (G) and pll pin3. goes to the TIP120 pickup (SIG_PRI), so you can say pin4. and pin3. are connected.

pll pin14. gets the signal from the feedback coil (H).
pll pin5. is the inhibit function (GATING)

Br,
Webmug

Quote from Webmug on May 15th, 2012, 01:59 PM

Quote from Faisca on May 15th, 2012, 09:26 AM

Quote

Which three?
I only refer to the Meyer!

Quote

1. PCT/US90/06407 patent (no TIP120 pickup, 4017, FB)
2. Dynodon photo circuit (TIP120 pickup, FB, no 4017)
3. RWG VIC1.0, VIC1.1 PCB (Sharky) (TIP120 pickup, FB, no 4017)

No switch or 4017 attached in the Photo at the PLL. Pll pin 4. is bypassed. pll pin 3 goes to the driver circuit.

Br,
Webmug

Quote

sorry I had not seen this picture yet.
If this is really original PCB S.Meyer I'm wrong, but where these wires are attached?
How did this stuff (pictures)?
Anyway are not linked together pins 3 and 4 in the PLL, right?
Thank you.

http://open-source-energy.org/rwg42985/russ/Stans%20Estate/meyers%20pics%20%2863%29.JPG
http://open-source-energy.org/rwg42985/russ/Stans%20Estate/meyers%20pics%20%2868%29.JPG
More detail, the pll pin4. goes to the cell driver circuit (G) and pll pin3. goes to the TIP120 pickup (SIG_PRI), so you can say pin4. and pin3. are connected.

pll pin14. gets the signal from the feedback coil (H).
pll pin5. is the inhibit function (GATING)

Br,
Webmug

Ok I got, but not exactly together (almost), because that way the delay is discounted Q5 and Q6 (a few uS.).
The transistor Q5 is inverted (C / E), but I think everyone has seen it. It was Q6 2N3055 or TIP120?
All this material was found working?
He had not all been confiscated by the government? (Men in Black)
Sorry for my questions, I had not this information.
It is noticed that there are several ways to do this work, but the main objective is: always catch the best frequency of the device, independent of any variable (temperature, capacitance of the cell and bubbles).
I will make changes in my prototype to see if it works better than before and I'll post.
I realized that with the algorithm (version uC) had no problems with gate. because the delay for a new lock is half cycle. But I do not know if this is good or bad.

Quote from Faisca on May 15th, 2012, 05:11 PM

Quote from Webmug on May 15th, 2012, 01:59 PM

Quote from Faisca on May 15th, 2012, 09:26 AM

Quote

Which three?
I only refer to the Meyer!

Quote

1. PCT/US90/06407 patent (no TIP120 pickup, 4017, FB)
2. Dynodon photo circuit (TIP120 pickup, FB, no 4017)
3. RWG VIC1.0, VIC1.1 PCB (Sharky) (TIP120 pickup, FB, no 4017)

No switch or 4017 attached in the Photo at the PLL. Pll pin 4. is bypassed. pll pin 3 goes to the driver circuit.

Br,
Webmug

Quote

sorry I had not seen this picture yet.
If this is really original PCB S.Meyer I'm wrong, but where these wires are attached?
How did this stuff (pictures)?
Anyway are not linked together pins 3 and 4 in the PLL, right?
Thank you.

http://open-source-energy.org/rwg42985/russ/Stans%20Estate/meyers%20pics%20%2863%29.JPG
http://open-source-energy.org/rwg42985/russ/Stans%20Estate/meyers%20pics%20%2868%29.JPG
More detail, the pll pin4. goes to the cell driver circuit (G) and pll pin3. goes to the TIP120 pickup (SIG_PRI), so you can say pin4. and pin3. are connected.

pll pin14. gets the signal from the feedback coil (H).
pll pin5. is the inhibit function (GATING)

Br,
Webmug

Ok I got, but not exactly together (almost), because that way the delay is discounted Q5 and Q6 (a few uS.).
The transistor Q5 is inverted (C / E), but I think everyone has seen it. It was Q6 2N3055 or TIP120?
All this material was found working?
He had not all been confiscated by the government? (Men in Black)
Sorry for my questions, I had not this information.
It is noticed that there are several ways to do this work, but the main objective is: always catch the best frequency of the device, independent of any variable (temperature, capacitance of the cell and bubbles).
I will make changes in my prototype to see if it works better than before and I'll post.
I realized that with the algorithm (version uC) had no problems with gate. because the delay for a new lock is half cycle. But I do not know if this is good or bad.

Referring tests:
I could only tune in sweeping by hand, with a potentiometer, because with these latest modifications (as discussed earlier), is only posivel, the best performance with dphi = 90 °. In this condition the phase comparator (CP2) does not lock and circuit detector is always indicating locking across the range of 300Hz to 20kHz. (all done without a pulse gate).
So I repeat, this is wrong!
Anyone got positive results and can show? (in thats way, such as)
Please.

Quote from Faisca on May 15th, 2012, 06:27 PM

Quote from Faisca on May 15th, 2012, 05:11 PM

Quote from Webmug on May 15th, 2012, 01:59 PM

Quote from Faisca on May 15th, 2012, 09:26 AM

Quote

Which three?
I only refer to the Meyer!

Quote

1. PCT/US90/06407 patent (no TIP120 pickup, 4017, FB)
2. Dynodon photo circuit (TIP120 pickup, FB, no 4017)
3. RWG VIC1.0, VIC1.1 PCB (Sharky) (TIP120 pickup, FB, no 4017)

No switch or 4017 attached in the Photo at the PLL. Pll pin 4. is bypassed. pll pin 3 goes to the driver circuit.

Br,
Webmug

Quote

sorry I had not seen this picture yet.
If this is really original PCB S.Meyer I'm wrong, but where these wires are attached?
How did this stuff (pictures)?
Anyway are not linked together pins 3 and 4 in the PLL, right?
Thank you.

http://open-source-energy.org/rwg42985/russ/Stans%20Estate/meyers%20pics%20%2863%29.JPG
http://open-source-energy.org/rwg42985/russ/Stans%20Estate/meyers%20pics%20%2868%29.JPG
More detail, the pll pin4. goes to the cell driver circuit (G) and pll pin3. goes to the TIP120 pickup (SIG_PRI), so you can say pin4. and pin3. are connected.

pll pin14. gets the signal from the feedback coil (H).
pll pin5. is the inhibit function (GATING)

Br,
Webmug

Ok I got, but not exactly together (almost), because that way the delay is discounted Q5 and Q6 (a few uS.).
The transistor Q5 is inverted (C / E), but I think everyone has seen it. It was Q6 2N3055 or TIP120?
All this material was found working?
He had not all been confiscated by the government? (Men in Black)
Sorry for my questions, I had not this information.
It is noticed that there are several ways to do this work, but the main objective is: always catch the best frequency of the device, independent of any variable (temperature, capacitance of the cell and bubbles).
I will make changes in my prototype to see if it works better than before and I'll post.
I realized that with the algorithm (version uC) had no problems with gate. because the delay for a new lock is half cycle. But I do not know if this is good or bad.

Referring tests:
I could only tune in sweeping by hand, with a potentiometer, because with these latest modifications (as discussed earlier), is only posivel, the best performance with dphi = 90 °. In this condition the phase comparator (CP2) does not lock and circuit detector is always indicating locking across the range of 300Hz to 20kHz. (all done without a pulse gate).
So I repeat, this is wrong!
Anyone got positive results and can show? (in thats way, such as)
Please.

Hi Faisca,

pll pin14. pulse 16.6kHz from my waveform generator as refIn I could lock-in with the circuit from Sharky. If the pulse was below or higher than the vco settings (R1,R2 C1-2) then the scanner is on free-run, no lock. (PLL VCO voltage min. to max. to min from the scanner)

https://www.youtube.com/watch?v=0VCLCG_6I18
You can see when I change the RefIn pll pin14. input signal in frequency the pll locks-in.
Blue is pll pin3. signal Yellow is pll pin4 Fout.
Second part is the yellow signal at the TIP120 SIG_PRI.

First I wanted to build the "cell driver circuit" from Stan but I can not make it work.
Perhaps you are able to make it work. For now I use the BC556 driver for the TIP120.

https://www.youtube.com/watch?v=s5KQn8oVDpo

Here you can see the Gating active, the pll tries to lock but it fails to keep it locked in the gate time and tries to lock-in again after inhibit is disabled. Yellow is the feedback signal from the opamp. Don''t mind the pulse shape it is not perfect! Should be 50% block pulse I guess.

All this I build on a breadboard. This is what I have so far...

Br,
Webmug

Quote from Webmug on May 16th, 2012, 02:23 AM

Quote from Faisca on May 15th, 2012, 06:27 PM

Quote from Faisca on May 15th, 2012, 05:11 PM

Quote from Webmug on May 15th, 2012, 01:59 PM

Quote from Faisca on May 15th, 2012, 09:26 AM

Quote

Which three?
I only refer to the Meyer!

Quote

1. PCT/US90/06407 patent (no TIP120 pickup, 4017, FB)
2. Dynodon photo circuit (TIP120 pickup, FB, no 4017)
3. RWG VIC1.0, VIC1.1 PCB (Sharky) (TIP120 pickup, FB, no 4017)

No switch or 4017 attached in the Photo at the PLL. Pll pin 4. is bypassed. pll pin 3 goes to the driver circuit.

Br,
Webmug

Quote

sorry I had not seen this picture yet.
If this is really original PCB S.Meyer I'm wrong, but where these wires are attached?
How did this stuff (pictures)?
Anyway are not linked together pins 3 and 4 in the PLL, right?
Thank you.

http://open-source-energy.org/rwg42985/russ/Stans%20Estate/meyers%20pics%20%2863%29.JPG
http://open-source-energy.org/rwg42985/russ/Stans%20Estate/meyers%20pics%20%2868%29.JPG
More detail, the pll pin4. goes to the cell driver circuit (G) and pll pin3. goes to the TIP120 pickup (SIG_PRI), so you can say pin4. and pin3. are connected.

pll pin14. gets the signal from the feedback coil (H).
pll pin5. is the inhibit function (GATING)

Br,
Webmug

Ok I got, but not exactly together (almost), because that way the delay is discounted Q5 and Q6 (a few uS.).
The transistor Q5 is inverted (C / E), but I think everyone has seen it. It was Q6 2N3055 or TIP120?
All this material was found working?
He had not all been confiscated by the government? (Men in Black)
Sorry for my questions, I had not this information.
It is noticed that there are several ways to do this work, but the main objective is: always catch the best frequency of the device, independent of any variable (temperature, capacitance of the cell and bubbles).
I will make changes in my prototype to see if it works better than before and I'll post.
I realized that with the algorithm (version uC) had no problems with gate. because the delay for a new lock is half cycle. But I do not know if this is good or bad.

Referring tests:
I could only tune in sweeping by hand, with a potentiometer, because with these latest modifications (as discussed earlier), is only posivel, the best performance with dphi = 90 °. In this condition the phase comparator (CP2) does not lock and circuit detector is always indicating locking across the range of 300Hz to 20kHz. (all done without a pulse gate).
So I repeat, this is wrong!
Anyone got positive results and can show? (in thats way, such as)
Please.

Hi Faisca,

pll pin14. pulse 16.6kHz from my waveform generator as refIn I could lock-in with the circuit from Sharky. If the pulse was below or higher than the vco settings (R1,R2 C1-2) then the scanner is on free-run, no lock. (PLL VCO voltage min. to max. to min from the scanner)

https://www.youtube.com/watch?v=0VCLCG_6I18
You can see when I change the RefIn pll pin14. input signal in frequency the pll locks-in.
Blue is pll pin3. signal Yellow is pll pin4 Fout.
Second part is the yellow signal at the TIP120 SIG_PRI.

First I wanted to build the "cell driver circuit" from Stan but I can not make it work.
Perhaps you are able to make it work. For now I use the BC556 driver for the TIP120.

https://www.youtube.com/watch?v=s5KQn8oVDpo

Here you can see the Gating active, the pll tries to lock but it fails to keep it locked in the gate time and tries to lock-in again after inhibit is disabled. Yellow is the feedback signal from the opamp. Don''t mind the pulse shape it is not perfect! Should be 50% block pulse I guess.

All this I build on a breadboard. This is what I have so far...

Br,
Webmug

Looks like you almost have it webmug.:cool::D