For Clarity http://en.wikipedia.org/wiki/Phase-locked_loop
Free Scale has a few Chips with this built in.
On most TA cards the PLL values used are as follows:
3.3nf 330pF and 3.9k
These seem to work fine, but aren't optimal according to Freescale or my calculations. If you experience clock issues, consider upgrading them to one of the following combinations:
3.3k, 6.8nF and 680pF (critically damped) Fred's arbitrary recommendation
3.9k, 6.8nF and 680pF (compromise for common values) Closest to TA values but with tighter damping
4.7k, 4.7nF and 470pF (compromise for common values) Freescale's recommendation
From Wikipedia, the free encyclopedia
"PLL" redirects here. For other uses, see PLL (disambiguation).
A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is 'fed back' toward the input forming a loop.
Keeping the input and output phase in lock step also implies keeping the input and output frequencies the same. Consequently, in addition to synchronizing signals, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency. These properties are used for computer clock synchronization, demodulation, and frequency synthesis, respectively.
Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz.
Structure and function
Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure. Both analog and digital PLL circuits include four basic elements:
Variable-frequency oscillator, and
feedback path (which may include a frequency divider).
There are several variations of PLLs. Some terms that are used are analog phase-locked loop (APLL) also referred to as a linear phase-locked loop (LPLL), digital phase-locked loop (DPLL), all digital phase-locked loop (ADPLL), and software phase-locked loop (SPLL).
Analog or linear PLL (APLL)
Phase detector is an analog multiplier. Loop filter is active or passive. Uses a Voltage-controlled oscillator (VCO).
Digital PLL (DPLL)
An analog PLL with a digital phase detector (such as XOR, edge-trigger JK, phase frequency detector). May have digital divider in the loop.
All digital PLL (ADPLL)
Phase detector, filter and oscillator are digital. Uses a numerically controlled oscillator (NCO).
Software PLL (SPLL)
Functional blocks are implemented by software rather than specialized hardware.
Neuronal PLL (NPLL)
Phase detector, filter and oscillator are neurons or small neuronal pools. Uses a rate controlled oscillator (RCO). Used for tracking and decoding low frequency modulations (< 1 kHz), such as those occurring during mammalian-like active sensing.
Type and order
Lock range: The frequency range the PLL is able to stay locked. Mainly defined by the VCO range.
Capture range: The frequency range the PLL is able to lock-in, starting from unlocked condition. This range is usually smaller than the lock range and will depend, for example, on phase detector.
Loop bandwidth: Defining the speed of the control loop.
Transient response: Like overshoot and settling time to a certain accuracy (like 50ppm).
Steady-state errors: Like remaining phase or timing error
Output spectrum purity: Like sidebands generated from a certain VCO tuning voltage ripple.
Phase-noise: Defined by noise energy in a certain frequency band (like 10 kHz offset from carrier). Highly dependent on VCO phase-noise, PLL bandwidth, etc.
General parameters: Such as power consumption, supply voltage range, output amplitude, etc.
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