One last note about this 5.0 board.
My biggest fear of this board being a failure is in regards to the input/output frequency ratio. I simply do not know if the frequency we are sending to the VIC should be a multiple or fraction of the frequency we see coming back via the feedback. If I had certainty some ratio exists, I would have added some ripple counters front and back of the PLL to allow for this. My hunch is there may be such a ratio, but I don't know what it is at this point. Once we determine if there is one and it has a fixed value, version 6.0 can incorporate the circuitry to implement it.
It's also possible the correct method isn't to implement a frequency ratio. It could be that we actually want the PLL to constantly overshoot/undershoot, continually hunting for lock. I just can't say at this point. I do know the more we experiment, the more variables we may find, but at the same time, the more variables we may solve. As long as we don't run out of time, resources or imagination, the solution will become apparent.