Quote from andy on March 10th, 2017, 07:23 AM

If we gate the PLL , when the gate time finish , what is the frequency from PLL to cell driver when PLL is ON again?

Keep in mind the VCO never stops running.  All the gate signal does is blank the output going to the driver transistors.  During this time the PLL may begin to drift (towards baseline) if no feedback is seen from the core.  If feedback is still present (the core is ringing), then the PLL will remain locked on frequency.

With no feedback the amount if drift is determined by how long the feedback is suppressed.  Long intervals will cause the VCO to reset all the way back to the base frequency of 1kHz.  Short intervals will allow the VCO to drift somewhere in between the current running frequency and the base frequency.  The low-pass filter network connected to the PLL determines how responsive this drift is.

Quote from Gunther Rattay on March 10th, 2017, 09:23 AM

a % of last frequency would be good to know. the longer the gating the more derivation will be. time for adjustment will depend on bit bang capacitor.

You could take the Application Notes PDF for the 7046 and run the numbers to get a good estimate.  The components used on this board seem to be a reasonable starting point.  I suspect once we have a cell running and we know the center frequency, all the components could be adjusted slightly around this frequency.

Your explanation is always great and helpfull Matt.
Thank you.

Quote from andy on March 11th, 2017, 09:45 AM

Your explanation is always great and helpfull Matt.

You are welcome.  Though I may be in error according to the logic diagram.

It's hard to tell if the inhibit pin is actually stopping the VCO or not.  If it actually stops the VCO, then when the inhibit signal is lifted, the VCO "appears" to pick up at the exact point where it was stopped.  It's possible though the VCO instead begins a new cycle.  This would likely create some jitter in the output.

What I do know is with the additional logic around the gating and inhibit, the pulses stream presented to the driver transistors is always 50% duty cycle.  There are no chopped or partial pulses when the inhibit pin is activated or when it is restored to normal running.

Quote from Matt Watts on March 10th, 2017, 11:26 AM

Here's the spreadsheet as you would send to Mouser.  You may want to remove the blank lines that separate the component types.

Thanks

Matt
Can you look on this:

Quote from andy on March 11th, 2017, 11:18 AM

Can you look on this:

In that logic diagram is sure looks like the inhibit stops the flip-flop.  So I would have to say when the inhibit is deactivated, the VCO starts a clean new cycle which may not be in-phase with the VCO output prior to the inhibit going active.  That would definitely create some jitter.

Question is:  Is that jitter harmful to the overall function?  Or more important, is it actually necessary, meaning the VIC needs this jitter to do what it does?  If it does, then the gating becomes rather critical to the overall operation.  Small changes in the delay and duration of the gating could make a huge difference in the behavior of the VIC.

Quote from Matt Watts on March 11th, 2017, 03:40 PM

Question is:  Is that jitter harmful to the overall function?  Or more important, is it actually necessary, meaning the VIC needs this jitter to do what it does?

By how much jitter (or latency or delay) does it become harmful?: 20 milliseconds, 100 milliseconds, 1 second? Is it harmful? Can it self-correct?

Limits are defined. If there is high frequency jitter, in an event that it is determined harmful, you would need a low-pass filter there to define a limit.

Quote from Matt Watts on March 11th, 2017, 03:40 PM

If it does, then the gating becomes rather critical to the overall operation.  Small changes in the delay and duration of the gating could make a huge difference in the behavior of the VIC.

What is the intended "behavior"?

You can hold a _stable_ PLL lock on a main carrier frequency, like a modern radio does, and still have jitter. If a limit is defined, "harmful" jitter would be mitigated.

A few cycles of jitter is nothing.

Jitter as long as 1 or 10 Hz is concerning. As well as 100 kHz of jitter.

A limit, or bandwidth, is defined.

Matt
When you gate the PLL can you zoom-in on the o-scope a few first cycles after gating is disabled , please?

The PLL should recover after an inhibit. I'm not sure what its behavior is after a few cycles looks like.

Quote from andy on March 11th, 2017, 11:28 PM

When you gate the PLL can you zoom-in on the o-scope a few first cycles after gating is disabled , please?

The gate logic that is preventing partial pulses is working properly.  Really hard to tell about jitter unless you are accurately tracking the phase angle.

Here's a couple of scope shots.  The first one would indicate to me the VCO is resetting; the second one ...?   Can't say.

This is running with actual core feedback, so it's a little dicey.

It certainly would be possible to re-arrange the logic a little to prevent the VCO from halting and restarting.  Whether this would be a worthwhile endeavor is hard to say.

The top trace is feedback from the core? Frequency top v. bottom trace?

Matt
Where was connected the probe of o-scope at?
Thank

Quote from andy on March 12th, 2017, 12:47 AM

Where was connected the probe of o-scope at?

Directly across VIC primary.  Signal is much cleaner upstream of driver transistors.

Quote from haxar on March 12th, 2017, 12:45 AM

The top trace is feedback from the core? Frequency top v. bottom trace?

Just a snapshot zoomed, centered on the gating.  Looking at two consecutive gate signals.

Thank you Matt

Matt
Can CD4098 replace CD74HCT221 for +12V operation? For gate generator?
Thank

It can be, but I caution using a retriggerable monostable multivibrator.  I have many SN74HCT123A chips and found out the hard way what their limitation is.

Quote from Matt Watts on March 14th, 2017, 02:54 PM

It can be, but I caution using a retriggerable monostable multivibrator.  I have many SN74HCT123A chips and found out the hard way what their limitation is.

The original VIC circuit has a 74122 IC as a monostable multivibrator, same as the 74123, to adjust the gate.

It would be helpful to know what the limitation is, and propose a better solution.

Quote from haxar on March 14th, 2017, 02:57 PM

It would be helpful to know what the limitation is, and propose a better solution.

The difference being retriggerable versus non-retriggerable.  The non-retriggerable variant I find to be more useful for deterministic pulse generation because it delays a predictable amount of time regardless of incoming trigger signals--only the first trigger matters.  Granted in a looped dual configuration like used here in this driver board, either method works fine since you are guaranteed to only get one trigger.  But in other applications, you may not have this guarantee, so the pulse width or pulse delay may get extended when the chip gets multiple triggers that fire before the time delay has expired.  When you see this on the scope for the first time, you'll question whether your duration time is working as you have set it.  The answer is yes, it is, but is now non-deterministic because you have multiple triggers.

Bottom line:

• Retriggerable -- uses the last trigger seen; looks at every subsequent trigger as a restart until the cycle is able to complete.
• Non-retriggerable -- uses the first trigger seen; ignores any triggers after this until the cycle completes.

Depends on what you want to do.  In my experience the non-retriggerable one-shot is more useful overall.

Matt
What is direct replacement for cd74hct221 from CD 4000 series , for 12V supply operation?
Thank Matt

I'm not convinced there is a direct replacement.
This is probably your best option:  http://www.ti.com/lit/ds/symlink/cd14538b.pdf

Thank you Matt

Gentlemen, be advised: this thread has been forked. Link here. The goal of this new thread is to get an exact count of people interested in ordering a VIC v5 driver board.

Kind regards,
Henne

Hi guys,

Something interesting came up on youtube last week. I'm sure you are all familiar with Valyonpz and his Youtube channel.

https://www.youtube.com/watch?v=qQVtFjE40zk

He did an analysis of Andrija Puharich`s AM Waveform, and also compares it to Stan's similar gated square block waveform. What is different however is that Andrija Puharich used one extra AM modulation of the overal signal in which it's modulated over +- 3 seconds where the signal goes from 0% to 100%. This cycle corresponds to the "nuclear spin relaxation time of water".

I don't know if this has an influence on gas production at all. However, it seemed relevant to perhaps consider this functionality for a next iteration of the board or manual addition to the current setup, for testing purposes.

I guess we'll cross that bridge when we come to it. :) The focus is obviously first on testing the current version, but I thought I'd share this now to ponder about. :)

With regards,
Henne