I might have got the driver circuit working correctly in multisim?

The resistor that comes from +10V to the base of Q6 will not allow the circuit to work unless it is over 1k but if it's that high disconnecting it altogether is no different. If not the Q6 transistor gets more current from the resistor off the +10V than it does from the incoming signal and then a continuous DC voltage passes through Q6.

The 470 and 1k resistors I kept the same but then changed the base resistor at the TIP120 to 4.7k.

I am getting the classic gated waveform now but no DC bias?

The only way I can get a DC bias is by adding a resistor from the primary coil +V to the base of the TIP120.

The inductor and resistor plays a big role in getting it to work. Try Stan's value of inductance of the primary and put the 220 ohm resistor in the circuit also.

So I did a sim and swapped two resistors (47K and 470).  When I run it with scope connected to the base of the Darlington (which I can't simulate very well), I get some crazy negative spikes.

Thoughts?

And when I connect to the output of the final drive transistor, I clearly have a DC bias offset, with a hard zero spike on the trailing edge of each pulse.

That's not normal guys and probably why Stan did it the way he did.

We need to get this on a bread board and see the same thing on a live scope.

I'll try to breadboard it later tonight....I'll post my results.

Oh good. You got some where Matt.

At least some one did. I see you had to stop values tho. That's ok. I'll re configure the one I made and test it.

If you move the scope along from transistor to transistor, you can see how that signal is built.  Pretty neat if I do say so.  Seems to stay pretty consistent in the frequency ranges mentioned in the patent.  A poor rise/fall time on the input kind of makes the little tail disappear as I would expect.

The zipped file for MultiSIM BLUE is attached if anyone wants to play with it.


I didn't try playing with resistor values too much--it looks mostly like the transistors themselves propagate and amplify that effect.  I can maybe try adding the high-side circuit too and see what everything looks like running as one unit.  Getting a little tired for today though--may half to sleep on it.

Quote from Matt Watts on December 11th, 2016, 06:13 PM

And when I connect to the output of the final drive transistor, I clearly have a DC bias offset, with a hard zero spike on the trailing edge of each pulse.

That's not normal guys and probably why Stan did it the way he did.

We need to get this on a bread board and see the same thing on a live scope.

Matt
It is not the DC bias.
It is voltage accross the diode and junction collector-emiter of the TIP120 in series when TIP120 is turn-on.
andy

Quote from andy on December 11th, 2016, 11:44 PM

It is not the DC bias.
It is voltage accross the diode and junction collector-emiter of the TIP120 in series when TIP120 is turn-on.

You have a good eye andy.    ;)

So lets take a look at the signal directly across the light bulb (load).

Well.

I had a busy weekend and couldn't get to breadboarding the vic driver. Hopefully some time this week?

Matt. Please give more info on your SIM

You have stated "switch R2 and R7"

Are the values on the resistors in that sim schematic corect? Are those "switched"

Also what voltages is your Sig gen set at? And dc offest?

I can't even get the first stage to go unless I drop the voltage of the first leg to 5v and the Sig gen past 7v

I'm wondering too if my Sig gen has the current needed to flip it on. I'm guessing yes.  Pluss that's what the second rest or is for. Current flow.

Ok well i officially started testing. I even cleaned my bench up really nice

~Russ

Ps. Ignore that 22k I could not ring a 1k around. Will get one in the morning. All my stuff is at work.

" for the love of stan"

Matt. Why are your load scope probes not connected to ground. Mesuring it the way you did would show a DC bias. From my thinking. ~Russ

Quote from ~Russ on December 13th, 2016, 12:08 AM

Are the values on the resistors in that sim schematic corect? Are those "switched"

How the heck should I know.  It seems to work and is pretty close to what Ronnie posted.

Quote from ~Russ on December 13th, 2016, 12:08 AM

Also what voltages is your Sig gen set at? And dc offest?

TTL.

Quote from ~Russ on December 13th, 2016, 12:08 AM

I can't even get the first stage to go unless I drop the voltage of the first leg to 5v and the Sig gen past 7v

Well it did work, but now that I have added the rest, it no longer runs properly and looks to me like the simulator can't figure out what to do with the components in orange (apparently no spice model).


Guess I'll just have to prototype the goofy thing.

Quote from ~Russ on December 13th, 2016, 12:35 AM

Matt. Why are your load scope probes not connected to ground. Mesuring it the way you did would show a DC bias. From my thinking. ~Russ

Andy is correct.  They must be connected where the actual primary coil would be.  And best I can tell, there is no DC bias there.  However, I'm not using a TIP120 component, because this silly simulator doesn't have one.  With an hfe over 1000, there might actually be some DC bias with the real thing.

Quote from Matt Watts on December 13th, 2016, 03:44 AM

How the heck should I know.  It seems to work and is pretty close to what Ronnie posted.

im sorry i must be confused, i was asking about the values on that photo of the sim are those what the sim is? or is there a " layer" where you tell the value?

TTL, 5V ok,

ill mess with it more tonight / tomorrow, 

its all good, its to funny that all us smart people are having such a hard time with this simple circuit. 

WE WILL GET THERE lets keep going,

one part at a time,

~Russ

Quote from ~Russ on December 13th, 2016, 09:33 AM

TTL, 5V ok,

The "G" signal coming from the PLL is probably a 12 volt signal, since PLL is a 4016 connected to VCC (12 volt).

All 4000 CMOS series chips can handle more than 5+ volts. TTL chips are only 5 volt.

Quote from Matt Watts on December 13th, 2016, 06:16 PM

The "G" signal coming from the PLL is probably a 12 volt signal, since PLL is a 4016 connected to VCC (12 volt).

That's why I asked what your Sig gen in your SIM was. Real life tells me it was more than 7 at least!!!

Hmmm...

Check this out.  Ten volt peak-to-peak output.

Well It works. As per Matt's #5 sim values.

However.
It only works With a 10vpk-pk signal. Will work from 7v to 12+v.   Below 7 and it's toast.


 5v on the first stage. It has a range between 2.5-6v. For the first stage. Any thing out side that range and it's tost.

For the third stage it works in most of the range 2-12+v it seems not to care to much.

Changeing any of the voltages dose not have to much effect on the Sig. Its quite nice through it. Also the first stage inverts the Sig. So an inverted input is directed on the first stage back to non inverted.


With a light as a load (aka resystor)  I see a DC bius. Even when mesured across the tip 120. Or the load.

However With a coil. There is no dc bias.  But my vic circuit is not complete correctly and I was using an iron core.

So theorticaly if it's impedance matched and the primary is seen purly as a resistance it could dc bias the primary? But only when everything is matched???

Sounds like we need to match a 1:1 transformer and see if it dc bias' 

That's would be a nice easy way to test the driver and an impedance matched load with out ever having a vic connected.

We need to think more like this if we can. Test each part and understand it. Then we can get to the more complex multi body problem of the "VIC" as a whole 

Zzz zzz...

~Russ

Good deal Russ.  I'll start a PCB design based on what we know now.

THE D.C. Bias you want at the primary comes when the diode short the primary such that the on time it will charge up but during of time it won't make in time discharging since the diode shorting the primary during off time makes a different time constant

First pass schematic including regulators and an input opto-isolator.  The opto-isolator is set to invert the signal and drives the first transistor with 10 volts which is what I think we decided is needed.  The pot (R11) is the voltage (power) control that allows you to tune the VIC starting at low voltage and adjust as you get closer to locking into resonance.  Having not tested the voltage control part yet, it may prove to be far too sensitive, so I'm guessing the 10k resistor on the Op-amp may need to be a trimmer to control the gain.  It's also possible we need both Op-amps in Figure 4 to achieve resonance, again just not sure.

Please check for obvious errors before I start designing the PCB.

Board will likely look something like the attachment image, but instead of header pins, I'll probably use PCB screw-down terminals such as:



The board needs a lot of work, so check out the schematic first if you would please.