Stanley A Meyer Legacy Teams
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PC9XE Sequential Gate Card
Figure 1: PCB Front
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Figure 2: PCB Back:
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Figure 3: Schematic
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74193:
The 74193 IC is a 4 bit binary counter (V+ to pin #16, 0V to pin #8). When a positive polarity digital input (positive square wave with 50% duty cycle) is applied to the COUNT UP (pin #5) a binary output is produced at pins #3, 2, 6, 7. Counting range is from 0-15 (decimal is 1-16). When count reaches 15, and another pulse is applied, the counter outputs will reset back to 0 and start over. In Stan's application, this counter was set up to count from 0-15 to sequentially move through 74154's 16 outputs. COUNT DOWN and LOAD are tied to positive supply voltage during operation. This prevents the count down function form being used.
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Pin #5, COUNT UP, is triggered via the first 7404 (pin #6). Pins #3, 5, 9, 11 are connected together. These are the inputs into the inverter stages. Pin #11 is triggered externally (goes out to bus pin). This means that the counting up occurs when the pin #6 changes state from LOW to HIGH.
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CLEAR (74193 - pin #14) is used to reset the counter back to 0. This function is used by Stan. When the counter is counting up, this pin has a LOW logic state which is provided by the 7404 (pin #2) via the HIGH digital output state of 74154 CH-3 (pin #4). CLEAR state changes to HIGH, resetting counter to 0, when output from 7404 (pin #2) changes from LOW to HIGH via the 74154 CH-3 being selected. When CH-3 is selected, the output goes from HIGH to LOW. Inverter chip inverts this LOW to HIGH. Since CH-3 is resetting the counter, it should be understood that Stan was only using 3 channels (0-2) of the 74154.
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74154:
The 74154 IC is an 16 channel De-multiplexer. Below is the 74154's function table. The chart shows the linear selection of output, corresponding to the 74193 counter's inputs (A-D). A-D are binary values that count up from 0 to 15 (1-16 decimal equivalent, 0-9, A-F binary). For every pulse to the "count up" pin on the 74193, the binary column is incremented. As can be seen, the binary value corresponds to what channel on the de-multiplexer's output has a logic change (LOW).
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Binary to Decimal conversion:
The column on the far left have two additional inputs, G1/G2. In the logic diagram, seen below, both of these have inverted logic (represented by dots on the inputs of the AND gate). Following the output wire, it can be seen that output is wired to an input of all the AND gates that determine which output is active. In Stan's application, this output needed to be maintained HIGH. This is accomplished by connected both pin #18, #19 to ground, providing LOW logic polarity to both inputs.
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7404-1:
Channels 1-3 (0-2 binary) of the 74154 send LOW logic signals (when triggered via 74193 count value) to the second 7404 inverter chip. The 7404 IC has V+ to pin #14, 0V to pin #7.
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CH1 (binary 0) -- 7404 pins #1, 13 (LOW logic state) --- 7404 pins #2, 12 (HIGH logic state)
CH2 (binary 1) -- 7404 pins #3, 11 (LOW logic state) --- 7404 pins #4,10 (HIGH logic state)
CH3 (binary 2) -- 7404 pins #5, 9 (LOW logic state) --- 7404 pins #6, 8 (HIGH logic state)
Pin #10 triggers one of the green LEDs. Pin #8 triggers the amber LED. Pin #12 triggers the other green LED. These would give a visual indication of what channel is currently selected. Pins #2, 4, 6 go out to another 7404.
7404-2:
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7404-1 Output Pin #2 -- 7404-2 Input Pins # 1, 3
7404-1 Output Pin #4 -- 7404-2 Input Pins #11, 13
7404-1 Output Pin #6 -- 7404-2 Input Pins #5, 9
7404-2 Output Pin 2 -- H11D1-1
7404-2 Output Pin 4 -- H11D1-2
7404-2 Output Pin 6 -- H11D1-3
7404-2 Output Pin 8 -- H11D1-4
7404-2 Output Pin 10 -- H11D1-5
7404-2 Output Pin 12 -- H11D1-6
https://stanslegacy.com/link/195#bkmrk-because-inputs-of-th Because inputs of the 7404-2 are in pairs, the outputs will be synched. This means that 2 pairs of H11D1 will be triggered at the same time. Six optocouplers total. 1 pair triggered at same time. This would allow a 3 phase H bridge arrangement possibly.