Phase Lock Circuit K21 testing issue.


Phase Lock Circuit K21 testing issue.
«  »Last edited
I have almost finished by testing of the Phase Lock Circuit K21.  I had lots of problems with this circuit some due to lack of component values mainly on the capacitor which I have resolve.  Found posts with correct values in this forum I have a link to that in the report I am writing.  Thing I still having issues with is the (A) signal input.  I can get it into the circuit but can not get the pulse past the first stage 4001.  At first I though it was because signal was not going completely low and that the Zener diode would fix this issue.  It did drop the signal offset to zero but did not solve the issue.  I got side tracked working on other parts of circuit and testing other functions. I had check if signal input is high output of 4001 goes low and stops signal.  Normal state was High which is what you want for VCO to work so I went on to test and checking other things which took quite a while.  Never finished checking impact of the (A) gate. 

When I tried to do that I found I still could not get the (A) signal to switch the 4001 from high to low.  Turns out signal from K3 is not large enough to cause the 4001 to switch.  My testing shows it needs to be around 7 volts to get it to pass the gate pulse.  But its only about 4.6 volts and only when I switch the 2.2K resister show on the diagram from ground to +12V.  I did get it to work with a 39 ohm resistor but that really got hot burned the marking on resistor.  Also did not like the fact that the Zener diode was letting higher voltage back to K3.

I tried dropping VDD in to 4001 to 10 volts to see what would happen - first it did not let the (A) pulse through and it also dropped output signal level (G) to 11 volts from 12 volts as the signal output level is determined by VCC.

Kind of odd that there is that much of a mismatch on signal levels.  May have the output on K3 wrong not sure but that is a 5 volt board. I know those chips do not like 12 volts it burns them out did that!  Need to solve this problem it is now last test in my testing but not sure what to do as I do not like using that small of resistor as a pull up as it pulls to much current and voltage levels are already a big issue with K21 circuit.

I do have most of the analysis and test report done just need to figure out how to test this problem before I publish it.


Re: Phase Lock Circuit K21 testing issue.
« Reply #1,  »
Nice Earl.

it is interesting to read your intro on this one



Re: Phase Lock Circuit K21 testing issue.
« Reply #2,  »
I added the Analysis and Test Report document and picture of the lock frequencies with Math function showing phase relation to original post.  I am doing it now as I am mostly done and happy with results I have seen so far.  I will do more testing when I have time.  Biggest issue that I see is getting (A) signal interface working so I can see complete (G) signal.  I think I can fix this by using part of the circuit from K8 analog voltage generator is it turns signal into 12 volts I should not need final amplifier as dealing with CMOS levels.

As far as can tell all the rest of the interfaces worked though I do want to test (H) with the real signal not just my simulated one.

I do believe the decade counters have another purpose that the PLL function as I could not find a reason for them in this circuit.  My guess would during conditioning of cell.  They provide a means of outputting other frequencies without changing operation setup.  As Ronnie mentioned higher frequencies means higher voltages so they gives means of getting different voltages at flip of the switch.

Interesting I did not find a means of setting an upper limit on frequency unless to you set one using scanning range.  You might be able to this by settle the upper limit on scanning range near resonant frequency but normal you would put the resonance frequency in the center of your scanning range.

One big thing iI did get out this testing is your are not testing for frequency but for phase relationship of the resonance frequencies.  I remember reading several discussion but phase relationship in discussions on the VIC coils and chokes.

It also appears the voltage level of feed back signal is not a big factor as long as there is enough of a signal for system to find edges to do phasing tests.  So again  I am not sure from what I have seen is trigger to keep system from running away. Only way in this circuit would to find the frequencies that are just below resonance then set the front panel pot so voltage level to VCO is always below them then lock it.  Not sure this would even work it would also mean you resonant frequency would be the very end of you scan range rather in the middle where you would normally want it.  Its possible it is being done on the analog side by setting the gain upper limit.

I am almost done building and testing the basic circuits - I have to finish testing this one and then test the Pulser Indicator circuit K14. I have built that breadboard for it just not sure how I am going to test it.

I do hope people are finding these useful.  I built circuit just to see what they do and have learned a lot in doing that.  The reports were for me as they helped define what to test and how I was going to do test.  What I have found is that the report also makes a great trouble shooting tool because my testing method of capturing the signal at each point in the circuit I can go back to report to see what signal should look like at those points.  I have had to do that a couple times when I damage things. I need to stop hooking up the wrong voltage or every worse hooking up  + voltage to ground. sadly I done that more than once.

I do have some family comments coming up that will keep me away for while.  So I am not likely to get to test K14 and finishing test this board until they are done.


Re: Phase Lock Circuit K21 testing issue.
« Reply #3,  »
be interesting to see the document 


Re: Phase Lock Circuit K21 testing issue.
« Reply #4,  »Last edited
It's attached to original post in this thread. Still not use to adding attachments to addition messages.  Finished hard wiring half the circuit this morning.  I had to build it on two boards as it would not fit on one board.  This is the side I knew would not change with (A) input fix.

Dan I think you reported multiple people have it system working has anyone documented step they used to condition cell to get it going?
Posted: July 9th, 05:15 AM

On a bread board I built everything in circuit Analog Voltage Generator Circuit K8 from input through the first 2 amplifiers Q1 and Q2 including the 2 resistors on the output of Q2.  This the part of the circuit I built.  Looks like it going to exactly what I want.  Will need to hook everything back up to test it though as I put everything away. But at least this is an easy fix if it works.

Converts 3v signal into 12v signal using 6 resistors and 2 amps.

Yellow trace is the Signal (A) out of K3
Blue trace is the output of test circuit after 1K on output before 47K pull up.
Re: Phase Lock Circuit K21 testing issue.
« Reply #5,  »
I track the Gate Pulse raised to 12V all the way through circuit from input until it reaches pin 5 on the CD4046B.  It now does what I expect as output of the first stage of 4001 now matches the input and output of second stages merges with (G) and there is a pulse sent to the inhibit input pin 5.  This pulse looks close to the (a) signal and that is what I would expect.  Before making this change it was always a flat line.

Went back to look at signal (G) which is not the combined Gate and Carrier signal. VCO generated output now has the gate pulse in it.
The good news is the signal has the Gate pulse in it the bad new system is now having a very difficult time locking. 
The bad new is that a pretty good lock is now very poor.  I expected this as Matt Watt had reporting in his testing of this circuit and new version, he is building that the gate interfered with the ability of the system to find and lock on resonance.

One thing I notice before fixing gate is that while the system is solid lock as you can see from this picture is the phasing spikes are on the leading and trailing edges and that they do not move around much but system still drops out of lock every 8 seconds.
What is interesting is that with gate in system the opposite happens.  The system only enters lock every 8 seconds then only briefly.
I did find a few articles that talked about an 8 sec problem with some PLL devices.  They were talking about using additional circuits to fix issue.  Seems to be a problem when you have a strong lock with sharp edges.  So, I am not sure this is caused by something the 4046 or by the control wave train created in K22.
With the gate pulse working I if a put the gate pulse on screen and trigger on it you can the gate in the (G) signal.  If you also turn on the Math function you can see the out of phase as well.  If I turned the scale on scope to show high frequencies and then adjust gate width on K3 you can see effect of gate on combined pulse train so that part of system is working the way in is described in Stan’s documentation.
Best way to see the pulse effect and is to stop the scanning control pulse is by putting K22 in manual mode and set the frequency using the Manual Freq Adjust Pot.   Now if you vary the pulse width using VIC Gating Adjust on K3 you can easily see the gate size changes.

I tried several things trying to get system to lock while gate pulse was present.  Setting the gate frequency to real low values seemed to the biggest help.  Every once in a while, you could see the frequency of the (G) signal flash on scope screen.  Most of the time frequency was below 1KHz.  I looked like it was scanning is too slow for it to get higher frequencies then a gate would appear, and it scan would continue.  Then 8 seconds would occur then a faster scan would happen, and you would see a brief lock then back to slow scan.
I tried to adjust frequency and the center point, and nothing seemed to make lock better when gate was present.  Only thing that seemed to always work is stopping the gate by either disconnection it, pulling Zener or putting on 2.2K pull down resister, basically killing inhibit functions.
I was being to believe that the scanning control wave train being created in K22 was running too slow or not formed correctly (see picture below) as there is a large gap in-between each pulse.  If you look at data sheet for 4046 it show scanning pulse to triangle wave train.  I think this is what I am see every 8 sec as this would be a fast scan.

I when to bed thinking this is a problem that needs to be fixed. I woke the next morning with a different view.  What if this is the way it is supposed to work and why.  My test of K22 shows that the scanning control pulse wave train never stops, and it is not reset.  What does happen in lock it is switched out for (E).  When lock it lost the control pulse is switched back at what every stage it is at.  So, what you have is a constantly varying signal at a fix rate, no signal for long period and then short scanning pulse and cycle repeats constantly.  If voltage increases with frequency increases and decrease when frequency decrease aren’t you in effect generate a wave that varies from 0 to max value then back to 0 on a set cycle like the AM wave in Puharick’s patent.

Assuming this is what the system is doing how would you use it?  How about using it in the condition phase and with the decade switches to step through the conditioning step up in voltage on the cell.  Keep in mind that resonant lock on the cell is not your goal at this point getting the cell to point conditioning cell is. Ronnie Walker and others say scope is jumping all over the place when then look at the signal coming out primary coil.  Maybe this is what they are seeing.

I did do a quick check of what could happen in you feed output signal (G) back into (H) to see what would happen and I got immediate lock which you expect as they are the same signal not sure what you would see with real feedback.  Will have to wait until I get more of system working with real feed to see what really happens.

In process of adding this and more screen shots of this testing to report will update the report above when I get done.
Re: Phase Lock Circuit K21 testing issue.
« Reply #6,  »Last edited
Today I decided to look at the data a different way.  I had been using a constant 5KHz signal as my (H) input which means system was trying to lock on this.  As I was thinking about this testing this is not the real case as input frequency should be close to the output frequency is fed back from signal being put into coils.

I did do a quick check of what could happen in you feed output signal (G) back into (H) to see what would happen and I got immediate lock which you expect as they are the same signal not sure what you would see with real feedback.  Will have to wait until I get more of system working with real feed to see what really happens.

Test configuration I had CH2 of scope on Pin 4 of 4046 and Pin 3 hooked to (H) input and CH1 of scope.  Note: This also gave me output of switch effect on (G) as it also feeds back into ping 3 (more on this later).

When I did this, I get solid lock with this pulse train (It stayed in solid lock for the all the rest of my testing). However, I am still seen scan cycle every 8 sec.  Found cause of this later in testing but will report where here.  Check lock signal and had random spikes then decided to check (F) from K22 as I was in solid lock and should see a flat voltage except for every 8 sec. So thought must be something in K22 but then wonder why was it zero volts and (F) should be (E) when in lock.  I then checked them both together and the both changed in step so K22 not source.  I also check the Lock signal and it is not changing state so something in 4046 is changing the state of (E) every 8 seconds and causing a scan.  Voltage on (E) was low as phase difference is low.

Both signals on the screen are at 10-volts then jump to 12-volt during scan.

At this point is very easy see the effect of changing the gate pulse width as signal stays in lock even during 8 second scan.  What is not easy to see is the actual frequency to the carries pulses in (s) as the frequency the gate pulses are what is picked up by scope un less you zoom so you are mostly seeing only one pulse then scope picks of the carrier frequency.

Things change when you start using the decade devices.  All the above was done at 4X which bypasses them.

Turns out this is easier to do if you use decade counters and switch.  I did this for all 3 counters and will post screen shots in report. 

This one is the 1x one discount frequency of blue trace which is (G) as it is not accurate. The Yellow trace is Pin 3.  In I zoom in even further so I am inside the decade output pulse the G is around 5KHz.

At this point I am a lot more comfortable with this circuit.  Trying to the lock test with a fixed input (H) allowed me to learn several things and was useful but it also caused some problems especially when trying to focus on lock

Using PIN 3 as source gave me solid lock and allowed to test and see other things.  In some ways closer to real system in at least frequencies where in same range but does show the phasing issues you would see in real system.

As much trouble I had seeing the carrier frequencies inside the gate signal as scope keeps trying to lock on the gate frequencies test the other side of coils is going to be interesting.


Re: Phase Lock Circuit K21 testing issue.
« Reply #7,  »
Earl this is  a good way to look at the decade counters, thank you for yoru explanation of your test it helps us all  consider the PPL and the way it can grip


Re: Phase Lock Circuit K21 testing issue.
« Reply #8,  »
I did post updated version of Report in first post in thread.  It has all the screen shots from decade testing and using (G) feedback into pin 3 as (H).  System locked when I did this so you can see effect of gate on signal. Easy to see changes to gate POT on K3 when I did this.  Also you can see effect of the decade counters.

Just need to finish hard wired board and I have that half done and test already.  That with give me 7 of the 8 boards I planned on building.  Just Pulse indicator left and I already have bread board version of that already done. But really need coils to test that properly. While likely do so simple functional test mainly to check that amplifier is working.

I has been interesting and fun and I learned a lot.  Still have things to learn.  I now know what most of the controls do but not what to set them at though some like the K3 are apparent - you turn knob to far and signal goes away and LED goes out.  I also saw this in testing this circuit as this was one of the main things I want to see in this circuit.


Re: Phase Lock Circuit K21 testing issue.
« Reply #9,  »
Hmm I just open the pdf it is a nice read well layed out nice Work Earl

be great if you post picture back from 7  boards for people I am sure member here will try to 
replication and tesr based on your pdf



Re: Phase Lock Circuit K21 testing issue.
« Reply #10,  »
Should be able to post pictures of all the boards later today to tomorrow as I am almost done with building hard wired version.  I spent less than $500 on everything and that included by a new digital controlled soldering iron (I had scope and digital voltmeter as basic tools wire cutter etc).  Basic I need all to parts including wire.  I was able to find almost everything on Amazon and had most parts in a couple of days.  Hardest part was get the correct name to IC to do the search.  I did the bread boards as I did not want to deal with all the work of designing a real circuit board.  However, I did redraw all circuits by hand laid out close the way I was going to build them on the bread board.  That was real helpful as I built from them and used them to check both breadboard circuit and hardwire version as it was the same layout.  If someone wants copies of the layouts I could always scan them in to a PDF document.  They are not pretty but they were helpful. I did copy real chip layout and used that in word document to print out the chips located near where they would be and then added connections and other parts in the locations I was going to put them.
Re: Phase Lock Circuit K21 testing issue.
« Reply #11,  »Last edited
Pictures of finished boards. I finished moving components for the Phase Lock board to hardwired boards.  Needed 2 cards as everything would not fit on one.  I also took a couple of pictures of all eight boards together.  The top 2 on right are the Pulse Indicator which I have not tested yet but this should be its final form.  The breadboard behind it in back is the circuit I built to raise (A) to 12 volt levels. I will put it on one of the other boards either the Cell Driver or the Pulse Indicator as there is extra room on both.

Everything has been tested except the Pulse indicator circuit and  they all work with the few minor changes I have made where things did not work at all.  These changes are all documented in Reports I have published in here.

Came a long way since I start reading in April.  However, I have lots of time as I am retired and was looking for something to do.  Next step is to finish Pulse board should not take long to move it to final board then build something to hold all these that has more permanent power hookups.  I have been using temporary cables using power plugs you see on back of boards.  They work well but it is sure a mess and too easy to hook them up wrong - managed to do that a couple of times.

After I do that it will be time to start thing about coils and a better power supply.


Re: Phase Lock Circuit K21 testing issue.
« Reply #12,  »
this is very nice  Earl thank you it is nice to see  as it fortifies the work to see pics Great Stuff

Re: Phase Lock Circuit K21 testing issue.
« Reply #13,  »
Photocopy can work
If you photo copy or scan boards it would be great than people
can try same layout actually you lay is better as people can see the function of each section



Re: Phase Lock Circuit K21 testing issue.
« Reply #14,  »

I scanned my working layouts and put them in the attached pdf. I had not indented to publish them in this form but they are what I used to built the bread board circuits as you need to know where the pins are located on the chips. I download pin out for each chip and then drew connections around them.  After building board I double checked all connections again these drawings and also back against original circuit drawings.  A lot of layout was driven by they way bread boards are made which both helped and hurt at times.  But it was an inexpensive way to get something built.

When I did testing I referenced items in report back to original circuit.

I do not have time right to do create better drawings and while I could do that it would be several days of work to do a good job.  I think I have posted pictures of all the finished boards along with report if I missed some I can go back and do that.  Note:  Almost all the connections where done on the tops so I could see them and where they go though few are so close it is hard to tell.  The attached drawings show chip pin connections which covers most of them.  In some cases where single point has multiple connection with either ground or power it was easier to just connect to them with multiple wires as you get the same affect.


Re: Phase Lock Circuit K21 testing issue.
« Reply #15,  »
Thank you Earl  , Every Little and big step helps

I am sure we can find some one with skills to help get these done in eagle  cad or diptrace and posted here
Great Work , remember it only takes  1 bright spark to light a box of matches we all try to  push that moment.
the world need the technology to come forward.

great to see the lay out it helps visual it better , invite to all to assist here as earl doing  good testing  and tuning here